1. Field of the Invention
The present invention generally relates to deposition of a metal layer. More particularly, the present invention relates to electrical contacts used for layering a metal onto a substrate.
2. Description of the Prior Art
Sub-quarter micron, multi-level metallization is an important technology for the next generation of ultra large scale integration (ULSI). The multilevel interconnects used in this technology require planarization of interconnect features formed in high aspect ratio apertures, including contacts, vias, lines and other features. Reliable formation of these interconnect features improves acceptance of ULSI, permits increased circuit density, and improves quality of individual substrates and die.
As circuit densities increase, the widths of vias, contacts and other features, as well as the width of the dielectric materials between the features, decrease considerably; however, the height of the dielectric layers remains substantially constant. Therefore, the aspect ratios for the features (i.e., their height or depth divided by width) increases. Many traditional deposition processes, such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), presently have difficulty providing features having aspect ratios greater than 4:1, and particularly greater than 10:1. Therefore, great amount of ongoing effort is directed at the formation of void-free, nanometer-sized features having high aspect ratios of 4:1, or higher. Additionally, as feature widths decrease, the feature current remains constant or increases, resulting in increased feature current density. Such an increase in current density can damage components on the substrate.
Elemental aluminum (Al) and its alloys are the primary metals used to form lines, interconnects, and plugs in semiconductor processing. The use of aluminum results from its perceived low electrical resistivity, its superior adhesion to silicon dioxide (SiO2), its ease of patterning, and the ease of obtaining it in a highly pure form. However, aluminum actually has a higher electrical resistivity than other more conductive metals such as copper. Aluminum can also suffer from electromigration leading to the formation of voids in the conductor.
Copper and its alloys have a lower electrical resistivity and a significantly higher electromigration resistance than aluminum. These characteristics are important for supporting the higher current densities, resulting from higher levels of integration and increased device speed, associated with modern devices. Copper also has good thermal conductivity and is available in a highly pure state. Therefore, copper is becoming a,preferred metal for filling sub-quarter micron, high aspect ratio interconnect features on semiconductor substrates.
Despite the desirability of using copper for semiconductor device fabrication, choices of fabrication methods for depositing copper into very high aspect ratio features, e.g. 4:1 or above, are limited. CVD deposition of copper has not developed and produces unsatisfactory results because of voids formed in the metallized copper.
Electroplating, previously limited in integrated circuit design to the fabrication of lines on circuit boards, now is used to fill semiconductor device vias and contacts. Metal electroplating, in general, is known and can be achieved by a variety of techniques. A typical electroplating technique comprises initially depositing a barrier layer over the feature surfaces of the substrate; depositing a conductive metal seed layer, over the barrier layer and then electroplating a conductive metal, preferably copper, over the seed layer to fill the structure/feature. Finally, the deposited layers and the dielectric layers are planarized by, e.g., chemical mechanical polishing (CMP), to define a conductive interconnect feature.
Electroplating is achieved by delivering electric power to the seed layer and then exposing the substrate plating surface to an electrolytic solution containing the metal to be deposited. The seed layer provides good adhesion for the subsequently deposited metal layer, as well as a conformal layer for uniform growth of the metal layer thereover. A number of obstacles impairs consistently reliable electroplating of copper onto substrates having nanometer-sized, high aspect ratio features. These obstacles include providing uniform power distribution and current density across the substrate plating surface to form a metal layer having uniform thickness.
One current method for providing power to the plating surface uses contact pins to electrically couple the substrate seed layer to a power supply. Present designs of cells for electroplating a metal on a substrate are based on a fountain plater (as shown in FIG. 1 as 10), including contact pins 56. The fountain plater 10 includes an electrolyte container 12 having top opening 13, removable substrate holder 14 that may be placed into the top opening 13, an anode 16 disposed at a bottom portion of the electrolyte container 12, and contact ring 20 configured to contact the substrate 48 and hold the substrate in position. The contact ring 20, shown in detail in FIG. 2, comprises a plurality of the contact pins 56 that extend radially relative to the contact ring 20, and are distributed about the contact ring 20. Typically, contact pins 56 include conductive material such as tantalum (Ta), titanium (Ti), platinum (Pt), gold (Au), copper (Cu), Titanium Nitride (TiN), or silver (Ag). Outer contact region 55 of each contact pin 56 extends over an outer peripheral edge 53 of the contact ring 20. The plurality of contact pins 56 extend radially inwardly over an inner peripheral edge 59 of the substrate 48 and contact a conductive seed layer of the substrate 48 at the tips of the contact pins 56. Inner contact region 57 of contact pins 56 contacts the seed layer (not shown, but included on substrate 48) at the extreme edge of the substrate 48 to provide an electrical connection to the seed layer. The inner contact regions 57 are configured to minimize the electrical field and mechanical binding effects of the pins 56 on substrate 48.
Substrate 48 is secured within and located on top of the electrolyte container 12 that is cylindrical to conform to the shape of the substrate, and electrolyte flow impinges perpendicularly on a substrate plating surface 54 of substrate 48 during operation of the fountain plater 10.
The substrate 48 functions as a cathode, and may be considered as a work-piece being controllably electroplated. Contact ring 20, shown in FIG. 2, provides cathode electrical bias to the substrate plating surface 54 resulting in the electroplating process. Typically, the contact ring 20 comprises a metallic or semi-metallic conductor. Because the contact ring is exposed to the electrolyte, conductive portions of the contact ring 20, such as contact pins 56, accumulate plating deposits. Deposits on the contact pins 56 change the physical electrical and chemical characteristics of the conductor and eventually deteriorate the electrical performance of the contact ring 20, resulting in plating defects due to non-uniform current distribution to the substrate. Efforts to minimize unwanted plating of substrate 48 include covering contact ring 20 and the outer surface of contact pins 56 with a non-plating or insulation coating.
However, while insulation coating materials may prevent plating on exposed surfaces of the contact pin 56, the upper contact surface remains exposed. Thus, after extended use of the fountain plater of FIG. 1, solid deposits inevitably form on the contact pins 56. Because of varied deposits upon different contact pins 56, each contact pin has unique geometric profiles and densities, thus producing varying and unpredictable contact resistance between contact pins 56 at the interface of the contact pins and seed layer. This varying resistance of the contact pins results in a non-uniform current density distribution across the substrate because of the resultant modified electrical fields. Also, the contact resistance at the pin/seed layer interface may vary from substrate to substrate, resulting in inconsistent plating distribution between different substrates using the same equipment. Furthermore, the plating rate is maximized near the region of the contact pins, and is decreased at further distances therefrom. A fringing effect of the electrical field also occurs at the edge of the substrate due to the localized electrical field emitted by the contact pins, causing a higher deposition rate near the edge of the substrate where the pin contact occurs.
Unwanted deposits are also a source of contamination and create potential for damage to the substrate. These deposits bond the substrate 48 to the contact pins 56 during processing. Subsequently, when the substrates are removed from the fountain plater 10, the bond between the contact pins 56 and the substrate 48 must be broken, leading to particulate contamination. Additionally, breaking the bond between the contact pins 56 and the substrate 48 requires force which may damage the substrate.
The fountain plater 10 in FIG. 1 also suffers from the problem of backside deposition applied to substrate 48. Contact pins 56 shield only a small portion of the substrate surface area, some electrolyte solution passes to the backside of the substrate (passing between the substrate 48 and the contact ring 20), thus forming a deposit on the backside and the substrate holder 14. Backside deposition may lead to undesirable results such as diffusion into the substrate during subsequent processing, as well as subsequent contamination of system components.
U.S. Pat. No. 5,690,795, issued Nov. 15, 1997 to Rosenstein et al., and assigned to the owner of the present invention (incorporated herein by reference) discloses a spring arrangement used to retain a shield in position without using screws. The springs are configured to permit electric current pass therethough while the springs are retaining the shield in position. In this prior art system, the spring is positioned remotely from, and does not interact electrically with, the substrate.
Therefore, there remains a need for an apparatus that delivers a uniform electrical power distribution to a substrate surface in an electroplating cell to deposit reliable and consistent conductive layers on substrates. It would be preferable to minimize plating on the apparatus and on the backside of the substrate, and also to minimize unpredictable plating of conductor pins.
The present invention relates to a contact ring used to apply electroplating to a substrate having an electrically conductive portion. The contact ring includes an annular insulative body, a conductive biasing member, and a seal member. The annular insulative body defines a central opening. In one embodiment of the invention, the conductive biasing member is configured to exert a biasing force upon the substrate. The conductive biasing member applies electricity to the electrically conductive portion when the electrically conductive portion is placed in contact with the conductive biasing member.